
A processor supports instruction pointer (IP) relative addressing in at least one operating mode of the processor. For example, in some implementations, IP relative addressing is supported in an operating mode or modes in which the address size is greater than 32 bits (e.g. up to 64 bits). In some embodiments, the displacement may be limited to less than the address size (e.g. 32 bits, in one implementation) when such operating modes are active. Code density may be higher than if the displacemen...











