A method of testing the performance of a combinational logic circuit is described. In contrast to a structural test which verifies the operation of the combinational logic circuitry, a performance test allows the performance of a combinational logic circuit to be tested by determining the accuracy of a set of outputs resulting from a change in input bits to the combinational logic circuit. Thus, it is possible to monitor more closely performance aspects, such as the maximum delay from input to o...

A scan register (80) provides for the decoupling of the scan data output signal (117) from the data output signal (116). This is provided through a tri-statable device (88), which is controlled by a scan enable signal or by the scan clock signal.

A scan method comprising a sensing photo module applicable in a scan apparatus for scanning a document is disclosed. The sensing photo module is equipped with photo sensors parallel to each other and detects the photo signal at every collection distance. The photo sensors extend horizontally and are positioned a line distance between the adjacent photo sensors. Under low operating resolution, the vertical resolution is increased by making the line ratio an integer, in order to solve the problem ...

The scan converter comprises first and second memories 3, 7, a frame memory 5; having a write period and a read period, a video data input circuit 2 for writing data at a first transfer rate into the memory 3, a video data output circuit 8 for outputting the data from the memory 7 at a third transfer rate. The transfer rate between the memories 3, 7 and the memory 5 is twice as fast as the first or third transfer rate, whichever is faster, and the memories 3 has data storage capacities greater t...

An integrated circuit comprises n storage elements, arranged to form a scan chain, that define m clock domains, wherein m.gtoreq.2 and n.gtoreq.m. A clock driver is adapted to provide m domain clock signals and m switching units, each adapted to provide one of the m domain clock signals to the storage elements in a respective one of the m clock domains in response to a first state of a scan mode signal, and to provide a single scan clock signal to the n storage elements in the m clock domains in...

A scan-on-read manager efficiently scans received data. The scan-on-read manager detects attempts by applications to read received data. The scan-on-read manager scans received data only responsive to an application attempting to read it. The scan-on-read manager only allows the application to read received data that has been scanned.

Described are a scan motor and a method of its manufacturing. The scan motor may include a static substrate; a dynamic substrate coupled to the static substrate via at least one flexible spring; a magnet coupled to a first side of the dynamic substrate; and a reflective element coupled to a second side of the dynamic substrate.

A scan module includes a scan motor, a laser; a sensor; and a mirror module. The mirror module includes (a) a collection mirror having an opening and (b) a fold mirror having a first end physically coupled to the collection mirror. A second end of the fold mirror is separated by a gap from the collection mirror.

A scan-on-read manager efficiently scans received data. The scan-on-read manager detects attempts by applications to read received data. The scan-on-read manager scans received data only responsive to an application attempting to read it. The scan-on-read manager only allows the application to read received data that has been scanned.

A device includes a scan circuit including a scan chain. The scan chain includes a first plurality of scan cells that receive a first scan clock signal in a first clock domain. A second plurality of scan cells receives a second scan clock signal in a second clock domain. A scan clock source generates the first scan clock signal and the second scan clock signal, and selectively inverts the first scan clock signal and the second scan clock signal based on an operating mode of the first plurality o...