
A shift register which is formed by a memory, the number of shift stages of the shift register is determined by the count value of a counter and designating a read address of the memory by a value obtained by subtracting an arbitrary constant from the count value of the counter through an operator. A multiplexer is provided at the input side of the operator. Output data, obtained by selecting a constant for determining the number of shift stages of the counter and a scan address in accordance wi...











