A semiconductor arrangement has an insulating protective layer composed of two sub-layers with a contacting window in the insulating layer, the outer sub-layer consisting, e.g. of Si.sub.3 N.sub.4 in the contact window is conducted over the edge of the inner sub-layer consisting of SiO.sub.2, up to the semiconductor surface within the window, so that the SiO.sub.2 layer is screened from the contacting electrode and the alien ions (Na-ions) usually contained therein.

A semiconductor device comprising a charge transfer device having a plurality of storage sites and a plurality of field effect transistors for reading the charge condition at a plurality of said sites. This is accomplished by locating the channels of the field effect transistors below the storage sites to be read and controlling or affecting the size of the channels by the amount of charge stored at the associated sites. Measuring the current through the channel thus indicates the charge level.

A hollow circularly cylindrical N semiconductor substrate includes a P layer disposed on its outer peripheral surface to form a PN junction in the form of a circularly cylindrical surface within the substrate. Two circularly cylindrical electrodes are fitted onto and into the substrate respectively.

A semiconductor device comprising a semiconductor substrate including at least three layers of alternating conductivity between a pair of principal surfaces, the side surface of said semiconductor substrate being formed in pulley-shape and the depth of the valley of the pulley-shape being selected from the most appropriate numerical range related with the dielectric constant of the surrounding medium and the thickness of the semiconductor substrate.

A semiconductor arrangement including a carrier plate which is provided w a slit-shaped recess for receiving the semiconductor wafer. The semiconductor wafer has a solderable contact electrode on each of its major surfaces and an elastic protective lacquer coating around its peripheral surface. The semiconductor wafer is arranged within the recess such that its major surface intersects the plane of the carrier plate and the protective coating of the semiconductor wafer contacts the end surfaces ...

A process for improving the reliability and solderability characteristics of plastic encapsulated semiconductor devices which includes the step of immersing the devices in N-methyl-2-pyrollidone.

A metal insulator-silicon field effect transistor is disclosed having an MNCNOS gate structure displaying semiconductor memory characteristics. The gate structure disclosed comprises at least one semiconductor layer comprising a plurality of clusters of a semiconductor material disposed over a first nitride insulating layer.

A semiconductor device wherein a beam lead connected to each wiring layer is all formed on a silicon nitride film of a semiconductor wafer surface in a semiconductor device having a multilayer wiring structure on a semiconductor basic board.

Two or more semiconductor device connected in series opposition and contacted by pressure contacts are enclosed in a common housing to form a surge diverter. The two diodes connected in series opposition are formed from a single semiconductor wafer exhibiting three layers whose conductivity types alternate from one to the next. The end faces of the semiconductor wafers have an edge concentration of at least 10.sup.19 atoms/cm.sup.3, preferable 5.sup.. 10.sup.20 atoms/cm.sup.3. The doping gradien...

A method of improving the voltage linearity of a semiconductor resistor for use, for example, in integrated circuit manufacture, which linearity is deteriorated by the loss of carriers in the resistor at the vicinity of a junction separating the resistor region from the semiconductor body. The method consists of bombarding the semiconductor to implant therein in the vicinity of the junction neutral ions, such as neon, forming lattice damage. The concentration of implanted ions and lattice damage...