An improved shared aperture sampler for high power laser beams includes a buried mirror positioned behind a dichroic reflective surface that reflects the high power beam and permits the sample beam to pass through and to be focused or deflected by the buried mirror.

A system and method is provided for providing security to components or assemblies employed by application programs during runtime. The present invention employs digital signature keys to ensure that an assembly name that is published is unique because the assembly is published with a publisher's public key. This prevents others from publishing an updated version of an assembly that claims to be published from the same publisher. The present invention guarantees name uniqueness and prevents name...

A method and apparatus for decoding signals received from a network and distributing the decoded signals to multiple users. A bulk decoder coupled to a network decodes data received from the network and transmits the decoded data to an interconnect for distribution to a plurality of users. The number and type of bulk decoders may be adjusted in accordance with system load.

A shared memory includes a plurality of multi-port memories each having at least one port with a copybus-function, and at least one port accessible from the user side. At least one copybus is connected to one of the ports with the copybus-function. The shared memory copies contents of one of the multi-port memories, which has been changed by a writing operation from the user side, to other multi-port memories through at least one copybus.

A method for controlling both shared and exclusive access for a resource in a multiprocessor system wherein a first-in/first-out queue is formed for tasks suspended while awaiting access and wherein access to the resource provides that control of access required for manipulation of the first-in/first-out queue which is not provided by the atomic nature of compare (double) and swap. Each member of the queue has indicators of the access it requested and of the next most recently enqueued member wh...

A shared data receiver for multiplexing and phase synchronizing pulse data from a plurality of data sources. An input multiplexer sequentially samples the pulse state of each data source multiple times during each received time period equal to a pulse interval. A transition detector detects pulse transitions in the sample stream from the multiplexer and uses this information to select phase synchronized samples from the multiplexer stream representative of the pulses from the data sources.

Disclosed is a hardware lock unit for limiting concurrent use of shared resources, such as segments of a memory, by a plurality of devices, such as processors, in a program controlled system. In such a system, devices wishing to use a shared resource make a use request to the lock unit by means of a memory READ command accompanied by an address that is associated in the lock unit with that resource, which each requesting device sends to the lock unit. The requesting devices then wait for an answ...

A shared memory technology where shared objects can be used by any of multiple users, applications, or program sessions with programming language support during development and at runtime. The developer can declare shared memory behaviors at design time to cause one or more area classes to be generated for use at runtime. A shared objects memory is managed by the runtime environment. Content is stored at runtime in an area instance of an area class. Class methods to be generated that include met...

A shared document feed station includes a common drive mechanism for normally advancing a receipt tape through a receipt tape zone and for selective operation to advance an alternative document through an alternative document zone. Document detectors sense the presence of a document in the alternative document zone and function to inhibit the drive mechanism from advancing the receipt tape while enabling the advance of the alternative document.

A processor system utilizing a single shared RAM array, for storing microcode and other function data, with the shared array coupled to the processor by a single shared ADR/DATA bus. In one embodiment, an onboard ROM stores selected lines of microcode and a ROM accessing system supplies microcode from the ROM when the shared RAM array is busy performing some other RAM function.