This specification describes arrays for performing logic functions. In these arrays input variables are placed on a series of parallel input lines that intersect a number of parallel output lines in a grid of intersections. Field effect devices at these intersections have their gate terminals connected to one of the input lines and their source terminal connected to one of the output lines and through a load device to a source of potential. The drain terminals of these devices are either unconne...

Circuitry implementing at least two amplitude level detectors and a method for monitoring their ability to track rapid changes in signal level is shown. The monitoring circuit uses a delay network to provide an indication that the detectors have not been driven into conduction during a specific interval of time. If this operation persists, a resetting circuit discharges the detector output filter network, thereby allowing the detectors to re-establish an output indicative of the present input si...

An incoming longwave infrared beam sharing the same aperture with an outgoing high power laser beam is separated from the laser beam path by a combination of a dichroic mirror and a diffraction grating.

In a data processing system including a relatively large, page-formatted memory, memory control functions are distributed over a plurality of microprocessors connected in an array with each microprocessor controlling a respective area of the large memory. Upon overflow of its assigned memory area, a microprocessor may "borrow" free memory space assigned to one of its neighbors in the microprocessor array. Memory control functions with respect to different areas in the memory can effectively be p...

By using a shared register directory having a bit array corresponding one to one to the processor for each shared register, a shared register control portion of a shared register control system in a multiprocessor system monitors to which processor each of the registers shared between processors is currently allocated or if it is not allocated to any of the processors at all (unoccupied condition), and allocates any arbitrary shared register in response to the request from each processor while a...

A control system for a balancing machine has a main computer with a keypad and monitor, an auxiliary computer for managing the balance measurement and correction functions and sharing the same keypad and monitor. Each computer controls the machine through a programmable logic controller (PLC). A video sharing circuit allows direct coupling of each computer to the monitor and includes a switching function under control of the main computer via the PLC to determine which computer will control the ...

A representation of a shared structured container type data object with related data bases can be used to present information in a hierarchy or multi-level mode about the activities and status relating to the shared container type structured data object and related data bases and its content of a plurality of structured data objects as well as other information affecting or tracking the shared container type structured data object content in multi-levels. Further, user access control also provid...

A memory array is provided which includes a common sense line to which is connected a first storage capacitor through first switching means and a second storage capacitor through second switching means, with a common word line connected to the control electrodes of the first and second switching means, a first bit line connected to a plate of the first storage capacitor and a second bit line connected to a plate of the second storage capacitor. Data is stored into or read from the first storage ...

A method and apparatus to control the flow of data from a plurality of independent turbine-generator data sources includes converting each serial stream of data from each source into parallelly formatted digital characters. These characters are stored in a dedicated buffer. When the buffer is full or when a specified time lapses for each partially filled buffer, the buffer is emptied through a parallel to serial converter into the data logger.

In a TDMA cellular network, there is provided a mechanism for shared-carrier frequency-hopping. It comprises: allocating on a frame basis within a reuse diameter to one coverage area during certain timeslot(s) at least one from a pool of TDM-frame-hopped carriers and allocating on a frame basis within that carrier reuse diameter to another coverage area during certain other, substantially non-overlapping timeslot(s) that frame-hopped carrier, all in substantially non-interfering time-synchronism...