An improved arbitration technique for a computer network system in which multiple nodes communicate using a shared bus. Each node in the system is assigned an initial arbitration number, N+1, where N is the node number assigned to the node. The arbitration number is the number of quiet slots a node must count before trying to transmit on the system bus. The length of a quiet slot is determined by a particular system's electrical characteristics. Each node in the system monitors a carrier signal ...

The present invention describes a circuit and method for utilizing a single dummy cell for each sense amplifier in a dynamic random access memory (DRAM) device. A precharge transistor connects a dummy cell capacitor to a reference potential and decoded selection transistors. The use of decoded selection transistors provides a means to share the dummy cell capacitor between either input of a differential or sense amplifier thereby reducing required area and circuit complexity.

A system for performing chemical analyses includes at least two analyzers and at least one peripheral device capable of serving either analyzer. A control system is coupled to the analyzers and to the peripheral device and selectively commands the peripheral device to serve one or the other of the analyzers depending upon the analyses requested for each analyzer and the analytical method applied. A control system providing sharing of peripheral devices in such a system is also provided, as is a ...

A linked list for multicast in an ATM network. The linked list comprises a first cell. The linked list also comprises a plurality of read pointers. Each read pointer is associated with a port. Each read pointer points to the first cell. A multicast system for an ATM network. The system comprises a first port through which a cell passes. The system also comprises a first read pointer associated with the first port. The multicast system additionally comprises at least a second port through which t...

In a shared contact electrically programmable read only memory, decoding circuitry is provided to prevent unwanted device programming due to sneak paths to ground. A two input NAND gate is coupled between adjacent column select lines. If either of the adjacent column select lines are energized, a data line will be enabled. Thus, for each column line energized, only two data lines will be enabled and only one of these will carry a voltage for enabling a memory device.

A general aviation navigational receiver is provided with a digital channel selection wherein a channel selection knob on the aircraft control board may be operated to control the functioning of a digitally implemented frequency synthesizer which in turn controls the operation of a voltage controlled oscillator for providing frequency signals to an RF mixer of the unit, the frequency synthesizer being programmed for both possible VOR/LOC and GS channel frequencies wherein switching between frequ...

A multiprocessor system is described which allows for the sharing of memories between the individual processors having synchronous memory interfaces. Three processing units are shown by way of example, each processor having its own local, associated memory. Two of the processing units can each access its own memory but not any other memory. The third processing unit can access its own memory as well as the memories associated with the other two processing units. An engine interface adapter inter...

A plurality of units under test (UUTs) are coupled to a plurality of programmable test instruments via a switching network, whereby the test instruments are shared by test stations each associated with a respective UUT. The test stations communicate with a processor via respective serial ports to execute test programs for testing UUTs. The processor controls the switching network via a parallel port to set up desired connections, and programs the test instruments, via a bus interface and a bus t...

A multi-processor apparatus is disclosed which includes an array of separately addressable memory units and an array of separately addressable processors. A first unidirectional bus delivers data from a selected processor to a selected memory unit. A second unidirectional data bus delivers data from a selected memory unit to a selected processor. Arbitor circuits control the flow of data to these data buses.

Two reflecting surfaces (102, 104) pass through each other at an intersection line (450) lying in a plane of symmetry (106). The two surfaces share a common aperture (101) and the surface contours of the two surfaces are preferably mirror images of each other and are arranged such that the respective two foci (110, 120) of the two surfaces are equidistant (108) from the center of the shared aperture and offset from each other in equal and opposite directions (109a, 109b) from the plane of symmet...