The inventive computer system uses a layer of software between the operating system and the hardware that localizes the fail-safe protocols into a single module. The system also uses shared memory allocation functions as the interface with the operating system. The memory allocation function creates data structures to satisfy the requests of the operating system. The system also has a data structure locking mechanism to prevent more than one processor from writing to the data structure at a time...

In a video conference system, participants are provided with a greater sense of presence. A pair of monitors are positioned at each location and provide a presence view image and a shared space image of the other location. With this system, participants can overlap their finger pointing at a shared image while maintaining eye-to-eye contact.

The invention relates to a method for maintaining coherency of software breakpoints in shared memory when debugging a multiple processor system. Using this method, at least two debug sessions associated with processors in the multiple processor system are activated. When a debug sessions sets a software breakpoint in a shared memory location, all active debug sessions are notified that the software breakpoint has been set. And, when a software breakpoint in shared memory is cleared by a debug se...

In a sense amplifier for detecting and amplifying a potential difference between a pair of signal lines (BM(BL), /BM(/BL)), a first pull-down circuit (N20, N21), a pull-up circuit (P10, P11), and a second pull-down circuit (N28, N29) are disposed in the recited order between the pair of signal lines. The pull-up circuit (P10, P11) includes a pair of p-type FETs (P10, P11) which configure a flip-flop, and the sources of the pair of p-type FETs are both connected directly to a first constant-volta...

A method, system, and computer program product for protecting data of a shared access data storage system from being overwritten, where the data storage system includes a device which is shared by separate hosts over at least two logically or physically distinct communication paths. An overwrite protection facility operates the data storage system controller processor independently of the hosts to automatically protect the device upon the occurrence of a write command for the device. The protect...

A shared peripheral controller including a primary bus interface, a primary bus first register, a shared bus interface, and a control unit. The primary bus interface is adapted to receive an operation via a primary bus, such as an ISA bus, from a first processor, such as a PCI-to-ISA bus bridge. The shared bus interface is adapted to communicate with a first shared peripheral, such as a real time clock, via a shared bus. The control unit is coupled to the primary bus interface and configured to ...

After amplification of a predetermined frequency component f.sub.0 +nfd of an intermediate frequency signal extracted by a mixer (44), a shared wave signal thereof is demodulated and modulated, thereby reproducing TDMA serving as a shared wave signal. Further, a subtracter (51) subtracts the TDMA serving as the shared wave signal from the intermediate frequency signal to extract CDMA#1 signal serving as a desired wave signal.

Apparatus for providing shared access to a shared RAM in situations where the shared RAM is electrically connected to a relatively slow address/data bus, and shared access is desired from a relatively faster address bus and data bus. An address buffer is connected between the address bus and the address/data bus, the address buffer for selectably buffering address information between those buses under control of an address buffer selection signal. A data buffer is connected between the data bus ...

This invention relates to a switch module for use in an asynchronous transfer mode (ATM) system incorporating a shared buffer memory where incoming data cells are stored and subsequently transferred to exit ports. An incoming data cell is stored at a vacant buffer memory address on an interleaved, word-by-word basis and the address is placed in an appropriate priority queue in the appropriate exit port for the data cell. When time is available for transmission from the exit port, the data cell c...

A method and apparatus for processing digital video data with a first processor and a second processor, wherein the two processors run asynchronously. First and second processor offsets are associated with the first and second processors, respectively. Commands for the two processors are stored in a set queue residing in memory shared by the two processors. The first and second processor offsets are compared to determine whether only one processor or both processors may implement commands.