
Disclosed is a shift register capable of mitigating gate bias stress. The shift register, including a plurality of stages, includes an output buffer having a pull-up transistor and two pull-down transistors, each with gates connected to different nodes. One of the two pull-down transistors operates during an even frame portion of an LCD operation; and the other of the two pull-down transistors operates during an odd frame portion of the LCD display operation. Alternating operation of the pull-do...











