State machines having a hierarchical arrangement of machines as between a parent state machine 10 and sibling state machines 11, 12, and 14. The parent state machine 10 generates a plurality of outputs constituting its output state as based upon its input state defined by inputs N and its internal state. Part of the input state is defined by a set of inputs 15 which include asynchronous signals such as reset and interrupts. The parent state machine 10 defines or partially defines input states as...

The invention relates to a method of managing a suspend state of a packet-switched service in a system which comprises a terminal (MS) and another peer (12), there being a packet-switched connection between the terminal and the other peer over which the terminal and the other peer transmit packets to each other. The terminal (MS) is able to use only either a circuit-switched service or a packet-switched service at the same time. When the terminal (MS) switches to the suspend state in the packet-...

A method of recovering the state of a system, which system comprises at least one counter, which counter represents an instantaneous state of an entity in a system. The counter will increase in value in response to an increment request and decrease in value in response to a decrement request, wherein each increment request is paired with a decrement request.

The subject of this disclosure is a Finite State Automaton (FSA) used as part of a term detector employed in a digital pattern search system (searcher). In particular the invention includes various advances in the art of FSA design which make the FSA practical for pattern recognition. Specifically, these advances minimize the amount of memory which is required in each FSA in performing pattern recognition, and allow a speed capability such that the searching can be performed at the rate at which...

A general purpose logic state analyzer selectively stores, formats and displays a digital signal representing a sequence of data states input thereto and provides a graphical display of the stored data states and a count of selected events occurring intermediate to the occurrence of the data states stored. Selective storage of the input data states is provided by comparing the input data states to a preselected sequence of first qualifier state conditions and enabling the storage of input data s...

The Solid State Step Transmitter converts a low level asymmetrical squareve voltage into a high level three-phase asymmetrical square-wave voltage, which is completely isolated from the input voltage and is one twenty-fourth of the input frequency. The output also has a positive and negative phase rotation selection.

A solid state color camera such as one-chip type CCD (charge coupled device) color camera having a color filter employed in association with the CCD chip and arranged so that an output signal derived from every other sequential line of scan includes only color component signals of the object being sensed.

Solid state imaging device wherein a plurality of picture elements each comprising a MOSFET and a photodiode connected to a source electrode of the MOSFET are arranged in rows and columns. The gate electrodes of the MOSFET in each row are connected in common, the drain electrodes in odd numbered rows and the drain electrodes in even numbered rows are connected in common, respectively within each column and connected to source electrodes of first and second switching MOSFET, respectively, arrange...

A solid state equivalent of a relay includes a pair of time delay circuits having inputs which couple to a pseudo coil terminal. One time delay circuit couples to drive a bilateral switch which simulates the operation of a set of normally closed relay contacts and the other time delay circuit is connected in series with an inverter gate and coupled to drive a second bilateral switch which simulates the operation of a set of normally open relay contacts.

A solid state imaging device capable of converting one-dimensional or two-dimensional optical information into an electrical signal is disclosed. A signal charge stored in each of a plurality of photo-electric converter elements, which is proportional to the amount of incident light, is read into a corresponding stage of a charge transfer device through a switching transistor under the control of a read control pulse. The read control pulse is applied through a clock line of the charge transfer ...