A bellcrank and control rod connection configuration achieving projectile damage tolerance through a combination of redundant pivots. Rod ends are connected to a bellcrank in a double pivot fashion so that should either pivot connection become disabled the other pivot connection will permit the maintenance of satisfactory control.

A radiation tolerant differential buffer amplifier provides amplification to small amplitude input signals. Circuitry is provided to selectively gate portions of the input signals for reduction of noise problems. Biasing circuitry sets a constant DC bias level for the amplifier to accomplish generally constant triggering of the amplifier.

A noise tolerant time division multiplex system including a transmitter and receiver, each constructed as a monolithic integrated circuit and interconnected by a serial data wire. Data as well as power is supplied to the transmitter from a plurality of parallel connected input switches. The transmitter includes a parallel in/serial out shift register controlled by timing logic and further includes a tri-state driver for generating a three-level serial output signal indicative of the status of th...

A fault-tolerant clock system for providng digital timing signals (system clock signals) is provided by a plurality of clock sources. Each clock source receives as inputs the generated clock signals from all the other clock sources and contains receiver circuitry to derive a system clock signal from said clock sources which is the consensus clock signals of the other sources. Each clock source generates and distributes to the other clock sources a clock signal which is phase locked to the derive...

An improved transmission line or waveguide that can tolerate damage from ordnance fragments without severe degradation of performance. Ordnance fragment penetration into a waveguide tends to produce jagged inward protrusions or loose metal chips of the type which can cause arc-over and high standing wave ratios. The present invention provides a transmission line or waveguide made of a brittle nonconductive material such as plastic or composite material which is coated on the surfaces bordering t...

A fault tolerant multiplier which utilizes a plurality of full adder rows has the ability to permanently deselect a row when a fault is detected in its initial testing. An extra row is provided to allow this deselection and transfer gates are provided between each row to shift the sum and carry logic on to the next row at the point of the deselected row and all rows therebeyond.

There is disclosed herein a fault-tolerant memory organization which permits through the incorporation of redundancy the utilization of circuit chips having defective sections. The apparatus involves the use of redundant sections fabricated on the chip in conjunction with a data relocation technique. The relocation scheme utilizes a code-decode arrangement which inserts zeros into the data stream to avoid the defective sections and provides a zero delete arrangement when the previously coded inf...

A decoding technique applicable to binary data encoded by phase encoding (PE), frequency modulation (FM), or modified frequency modulation (MFM). Resynchronization of the decoding clocking circuitry occurs upon every flux transition, rather than at less than all flux transitions, such as only at each data flux transition in the case of phase encoding. The technique provides substantially greater velocity tolerance than previous techniques for decoding codes encoded in this manner.

A logic gate is disclosed employing enhancement mode MESFET gallium arsenide devices which do not require the tight process control necessary in the prior art because two such devices are employed in the gate circuit to mutually compensate for the effects of their equal deviation from nominal threshold voltages.

The invention is a defect tolerant memory for a computer system. The defect tolerant memory has a main memory, a redundant memory and a mask memory. The redundant memory receives and stores data redundant to that addressed to defective cells in the main memory. The redundant memory has multiple memory levels and uses a randomness technique to store redundant data for all chips of the main memory. The mask memory stores the location of each defect of main memory and indicates when a defective wor...