The error tolerant arithmetic logical unit is divided into vertical bit-planes which are relatively independent, being coupled mainly for the purposes of shifts and carry propagation. The system tolerates failures and still functions correctly by reconfiguring the unit through the control of interplane connections. By inserting a spare bit-plane into the system and switching between bit-planes to bypass a failed plane, the effect of the failed plane or of a failure in a position of control logic...

A radiation tolerant relay control system having a threshold amplifier, bking oscillator and relay driver for actuating a relay winding. A flyback path from the blocking oscillator to the relay winding augments the duty cycle to insure that a predetermined number of input pulses occurring within a time period will energize the relay winding and effect relay operation.

A defect-tolerant memory system has means for determining when memory operations are addressed to locations that are defective, and for directing these operations to spare memory locations in a main memory. A content addressable memory is provided which has an argument section for storing the addresses of defective locations in the main memory, and a function section for storing a substitute address for each of the defective locations. When the content addressable memory determines that an addre...

In an improved control for a refrigerator, critical components such as fresh food and freezer compartment temperature sensors, temperature set devices and baffle are sampled to confirm that each is operational. Upon diagnosis of a critical component failure or of multiple component failures, the control, using stored control parameters, operates the remaining components in a manner that will continue to preserve food.

A memory array is organized into rows and columns of memory cells, each cell having a configuration which passes current or blocks current depending upon the state of that cell. The array includes sense circuits to sense cell state. In a preferred embodiment of the invention, an address signal sent to the memory array activates two sets of memory cells connected to the same sense lines, and the threshold level of the sense circuits is set above the level which would be sensed for a failed bit, s...

An improved storage device is provided for enhanced protection from fire and theft. It has advantages of lightweight for transportation and installation, heavyweight for protection when in use, steel construction for theft protection, dry insulation for heat flow retardation, fluid for limiting internal temperature rise and low cost. These capabilities are achieved by constructing a multi-walled storage device having an inner wall of steel for theft protection, an outer chamber of insulation to ...

A fault tolerant logic circuit capable of absorbing many D.C. and A.C. defects. The logic circuit employs a number of redundant logic gate circuits. The gate circuits are arranged in at least first and second interconnected signal paths. The logic gate circuits have two independent outputs. The two independent outputs are each connected to an input in a discrete one the first and second interconnected signal paths.

In a multiprocessor system interconnected by a bus structure that provides communication and information transfers between the processor modules of the system, each processor broadcasts a central message to all the other processors of the system on a periodic basis. A processor module not receiving the control message from a sending processor module will assume the sending processor module has failed, and operate to take over the task of the failed processor module.

When a fault is detected in a processor, program execution in this processor is interrupted and taken up again by a standby processor from an earlier uncorrupted state, a recovery point. Such recovery points are specially provided in the program. A save copy of the state at the recovery points is created in each case in a state save unit by recording changes compared with the respective previous state. The data memory existing in the state save unit has pairs of memory words, in which arrangemen...

Piston (25) and/or gland (20) structure for a hydraulic actuator (10) includes a plurality of deformable plate members (40, 45, 90 and 95) interconnected at a plurality of locations thereon by frangible fasteners (50). The fasteners are highly loaded in shear and fracture under conditions of abutment of the piston or gland with a ballistically damaged portion of the actuator thereby allowing the plate members to deform around the damaged portion, thus preventing jamming of the actuator.