A small programmable memory means such as an electrically programmable logic array is incorporated on the chip of a conventional bit addressable random access memory or other cell addressable array circuit. The array has one or more superfluous rows and/or columns of cells held in reserve. Processing and testing of the chip is conducted in a conventional manner. Chips with faulty cells are corrected by programming the memory means with the cell addresses of the faulty cell locations. Subsequentl...

A small programmable memory means such as an electrically programmable logic array is incorporated on the chip of a conventional bit addressable random access memory or other cell addressable array circuit. The array has one or more superfluous rows and/or columns of cells held in reserve. Processing and testing of the chip is conducted in a conventional manner. Chips with faulty cells are corrected by programming the memory means with the cell addresses of the faulty cell locations. Subsequentl...

A field-access, magnetic bubble memory organized in a major-minor configuration includes an extra set of minor loops dedicated to fault correction. The loops of the extra set are coupled to a major path in a manner to move the information in the loops of the set controllably out of synchronism with respect to the information in the remaining loops. Thus, information in the loops of the extra set can be inserted into the data stream originating from the remaining loops at positions of missing dat...

Methods for increasing defect tolerance and fault tolerance in systems containing interconnected components, in which a signal level is classified as belonging to one of a plurality of different, distinguishable classes based on one or more thresholds separating the signal-level classes, and defect-and-fault tolerant systems embodying the methods. An electronic-device embodiment including an array of nanowire crossbars, the nanoscale memory elements within the nanowire crossbars addressed throug...

In compression systems, a portion of the compressor outlet flow (28) is extracted and introduced through a surge nozzle (52) into a plenum (48) upstream of the compressor (14). The surge nozzle (52) is oriented so as to introduce in the fluid in the plenum (48) a vortex having the same axis and direction of rotation as the compressor rotor (54).

A multi-stage, alternate routing switching network is enhanced with a switch architecture that is able to detect and mask all single faults. The switch employs a controller that develops dual rail control signals. In one embodiment, the controller is made up of two controllers that receive the same inputs but generate complementary outputs. The complementary outputs form the dual rail signals that control the multiplexers that are interposed between the inputs and the outputs of the switch. The ...

A method and apparatus for providing a fault-tolerant backup system such that if there is a failure of a primary processing system, a replicated system can take over without interruption. The invention provides a software solution for providing a backup system. Two servers are provided, a primary and secondary server. The two servers are connected via a communications channel. The servers have associated with them an operating system. The present invention divides this operating system into two ...

The invention is directed to a jam tolerant ballscrew actuator. The ballscrew actuator is driven through a differential via plural power paths therein. A first of these differential power paths is drivingly coupled to a reciprocating dual ballscrew assembly by way of a rotatable ballnut. A second of the differential power paths is coupled to the dual ballscrew assembly via a rotatable hub having a splined opening therethrough. A reciprocating sleeve having a splined portion engages the sleeve sh...

A fault tolerant network for a plurality of computers includes a system for controlling access to shared peripherals. Access to the shared peripherals is coordinated among the computers by means of communication through a semaphore box. Each computer connects to the semaphore box via a channel. The semaphore box is comprised of two major sections: a semaphore section and an I/O section. The semaphore section contains two sets of semaphores: a first set comprising reservation semaphores for the s...

The present invention allows a data packet to reach its destination by automatically routing the data packet around failed components by means of a simple and efficient routing algorithms. The present invention is directed to a method and apparatus for routing a data packet through a series of ring stations, a series of mid-switch routing elements, and end-switch routing elements. An apparatus according to the invention includes a first series of ring stations and routing elements that are adapt...