In the present invention, fault containment module signals are assigned to the pins so that a band of guard pins connected to ground exists between the signal pins belonging to each fault containment module. Thus, a bent pin or foreign contaminant can only cause a short to ground or to another pin assigned to the same fault containment module, thereby diminishing the chance that bent pins and foreign contaminants will cause interference between the signals from different fault containment module...

The invention includes a new, cold tolerant strain of mycoparasite Trichoderma and mutants that are resistant to a pesticide to which the Trichoderma isolate is sensitive. These novel Trichoderma are capable of parasitizing fungi which are pathogenic to plants. They are also capable of producing proteinaceous, antimycotic substances which can inhibit the growth of plant pathogenic fungi. Cold tolerant Trichoderma and its biotypes can be used in, but not limited to, controlling fungal plant disea...

A memory system in which fault tolerance is achieved utilizing redundant clocks. The redundant clocks are synchronized, and a voter is used to deselect nonmatching clocks, thereby avoiding clocking errors. A circuit is provided to ensure a nonoscillating clock provides an output level at a desired state. Another circuit is provided to ensure oscillation upon power up.

An envelope follower is provided which reduces defect propagation when reading analog information signals from a read head of, for example, an optical drive or a magneto-resistive tape drive. In a preferred embodiment, the envelope follower includes a differential amplifier, to sense the difference between the amplitude of the information signal and an envelope voltage across a capacitor, and a current mirror, responsive to the differential amplifier, to charge the capacitor at a predetermined r...

A material 11 is protected from acoustic shock waves generated by impacting projectiles by means of a backing 12. Backing 12 has an acoustic impedance that efficiently couples the acoustic energy out of the material 11.

A reverse-flow fluid control system utilizes a pair of rivet-shaped flappers mounted on a motor driven lever to apportion fluid between a pair of nozzles. Each flapper is slideably mounted upon the lever to allow the lever to move relative to and independently of the flapper should a chip become lodged between a flapper and a nozzle as the lever moves towards that nozzle.

A fault tolerant computer architecture in which a functional unit is duplicated and the input and output signals to and from the two units are compared with each other by comparators to provide an error signal in case of different behavior of the two units, resulting in different input/output signals. The operation of both functional units is controlled by a first read only control memory or alternatively by a second read/write control memory once it has been loaded with microprograms, under con...

Circuit modules for providing digital or analog outputs from computational devices in such a manner that the components of the output circuit modules are tolerant of malfunctions in one or more of the components. In the digital output embodiment of the invention, output signals are independently derived using two voting circuits and are then applied to two switches connected in series to provide a fail-safe condition for most types of failure of the switches or the voting circuits. Two identical...

A microprocessor that detects and corrects random soft errors during program execution occurring in its storage elements (memory). Such a microprocessor utilizes a bit serial architecture and single error correction double error detection techniques that automatically detect and correct soft errors occurring in its internal memory elements during each word cycle. The microprocessor automatically detects and corrects soft errors during each word cycle. The error detection and correction is transp...

A fault tolerant smart card is provided having primary functional units including a standard ISO interface, a first microcontroller, a clock, and main memory. Secondary functional units including a secondary microcontroller, secondary memory with bit checking capability and an alternate battery power source are also provided. A microcontroller error detector is connected to both microcontrollers. Should a discrepancy between microcontrollers occur known test patterns are run on the second microc...