A field effect transistor is provided in which a drain current is not influenced by fluctuation of a gate voltage. In order to set the transistor in an on state (conductive state), a voltage equal to or more than a threshold voltage is applied to an inversion layer formation region (19) via a gate electrode (12) to thereby form an inversion layer. Charge inducted by the inversion layer moves to a channel region (18) and make the Fermi level of the channel region (18) fluctuate, and then, a poten...

A transistor comprises: an insulating layer; a semiconductor layer provided on a major surface of the insulating layer; a gate insulating layer provided on the base region; and a gate electrode provided on the gate insulating layer. The semiconductor layer has a source portion having a plurality of source regions of a first conductivity type and a plurality of base contact regions of a second conductivity type, the source regions being alternated with the base contact regions, a drain portion of...

A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor including a pair of impurity regions and a gate electrode 604 sandwiched therebetween, one of the impurity regions has respective contact holes (a first contact hole 601 and a second contact hole 602) and the other impurity region has a contact hole (a third contact hole 603), and contacts of the contact ...

A field effect transistor is provided in which a drain current is not influenced by fluctuation of a gate voltage. In order to set the transistor in an on state (conductive state), a voltage equal to or more than a threshold voltage is applied to an inversion layer formation region (19) via a gate electrode (12) to thereby form an inversion layer. Charge inducted by the inversion layer moves to a channel region (18) and make the Fermi level of the channel region (18) fluctuate, and then, a poten...

A transistor includes an NPN transistor provided with an N-type emitter, a P-type base, an N-type collector, an emitter diffusion region and a collector compensation diffusion region around the base and the emitter for decreasing a saturation voltage and a parasitic PNP transistor in a region where the NPN transistor is formed, the parasitic PNP transistor operating under saturation of the NPN transistor.

A delay element is introduced into a transistor-transistor logic circuit having a totem-pole-connected inverter transistor and an off-buffer transistor, in order to ensure a safe and correct operation even in the case where the transistor-transistor logic circuit is used as an element of multiple-connected transistor-transistor logic circuits.

Disclosed is a transistor-transistor-logic (TTL) circuit which is testable by D. C. Testing Techniques. The improvement includes a high impedance network for providing sufficient base drive to drive the output transistor into conduction when the malfunctioning input transistor fails to provide a turn-off logic level. The high impedance network can be a Schottky barrier diode and an epitaxial resistor connected in a series path between a potential supply and the base region of the output transist...

A transistor-transistor logic circuit, i.e., TTL circuit includes at least one input terminal (IN; IN.sub.1, IN.sub.2), an output transistor (T10, T1), and elements (1, 2, T11, T12; 3, 4, T2) operatively connected between an input terminal and the base of an output transistor. The elements include a plurality of delay parts, each having a different signal propagation delay time respectively which feed base currents to the base of the output transistor in and at a different times. As a result, a ...

A transistor arrangement, particularly for the fast switching of inductive loads, includes a driving first transistor and a power output second transistor (T1, T2) interconnected as a Darlington pair having a base terminal, an emitter terminal and a collector terminal. A third transistor (T3) has its collector connected to the base of the first transistor (T1) and its emitter connected to the emitter terminal (E). A fourth transistor (T4) of a conductivity type opposite to that of the first, sec...

Transistor-transistor logic, wherein a PN junction is formed in the semiconductor substrate to assure a sufficient transient current to flow when the two transistors at the output stage become transiently "on," said PN junction being reversely biased to exhibit a barrier capacitance and said capacitance being coupled in parallel with the circuit, thereby sufficient circuit operation and high reliability being obtained with a simple structure.