A MOS transistor having a capability for withstanding a higher surge voltage. The transistor comprises a high specific resistance region, a low specific resistance region located on the high specific resistance region and a well region located side by side with the high specific resistance region. The bottom surface of the well region comes in contact with the low resistance region, thereby breakdown current flows uniformly over a wide area.

A gate electrode (4') of a MOS transistor is formed in a depression (16) provided in a substrate (1). Source and drain regions (6 and 7) of the MOS transistor are formed in the substrate (1) to be opposed to each other with the gate electrode (4') being located therebetween.

An improved MOS transistor and method for making that transistor are provided. The improved transistor is characterized by decreased size, improved switching speed, and improved reliability in inductive load use. The improved structure is achieved through the use of a low minority carrier injecting source region formed, for example, by providing a low barrier height metal silicide. The metal silicide source provides a source of majority carriers but little minority carrier injection and hence li...

In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D' of the gate electrode 114 is set larger than a uniform thickness D of the gate electrode 114 on the gate oxide 112. A height difference A between a surface of the gate oxide 112 and a surface of the device isolation film 110, a width B of a step portion 110b of the device isolation fil...

A mixer for mixing first and second signals for providing a difference signal comprises a mixing transistor. The first and second signals are applied between the base and emitter electrodes of the transistor. A non-linear impedance is coupled in series with the emitter electrode. Spurious signal components are reduced in amplitude compared with the difference signal.

A semiconductor device comprises a semiconductor substrate, an active region positioned in a portion of the substrate and a field insulating layer surrounding the active region and partially embedded in the substrate. The semiconductor device according to the present invention further comprises an insulating member positioned under and attached to the bottom of the field insulating layer and surrounding the active region with the field insulating layer. Because of this insulating member, the thi...

In a lateral transistor having a first semiconductor region of one conductivity type, and an emitter region and a collector region both having the opposite conductivity type and disposed in the first semiconductor region; a second semiconductor region having the opposite conductivity type is disposed opposite to the emitter region with respect to the collector region. The thus obtained lateral transistor has a characteristic that a current flowing to the substrate is prevented under a saturation...

A power transistor according to the present invention improves breakdown resistance, in a monolithic structure for connecting a first-stage transistor and a second-stage transistor in Darlington connection, by constructing the same such that no parasitic transistor is substantially formed in the area for connecting the first-stage and second-stage transistors.

The specification describes a new MOS transistor structure in which the source gate and drain are formed within a trench in the semiconductor substrate. The gate width is determined by the depth of the trench and can be increased substantially without increasing the surface area occupied by the transistor. The result is a transistor with exceptionally high gain for a given surface area. Forming the transistor within and over a series of trenches further enhances this effect.

A bipolar transistor having higher conductivity semiconductor material in the substrate as compared to the active base region to provide charge generation disturbance protection.