An update synchronizer includes a two-stage synchronization unit for generating enable signals to select an output signal from among multiple input clock signals of a clock delay multiplexer. The enable signals originate from an asynchronous control signal having a phase different from that of the clock signals. A pre-synchronization logic stage transforms the asynchronous control signal into complementary synchronous control signals for use by the clock synchronization units; these synchronous ...

A method and apparatus for modifying data which is stored in a medium of hival quality. The original data is left unmodified, and a modification document is prepared which has addition and deletion data thereon. The original and modified data is combined in a given way to generate a correctly modified composite.

A system for updating an ECC code over a line in a data store when only part of the line has been updated is described. The system receives the update and its address, decodes the address to generate a first signal identifying the part of the line to be updated and a second signal identifying an un-updated part of the section. The data of the update and the first signal are used to generate a first partial error code. Data from the un-updated part of the line is read as the update is written to ...

Loop gain normalization is employed in adaptive filters to control weighting of the filter characteristic updates in order to converge properly to a desired filter characteristic. Filter stability and rapid high quality convergence is realized for a variety of received or inputted signals by employing both long term and fast attack estimates of a prescribed input signal characteristic to normalize the update gain. In one embodiment, both long term and fast attack input signal power estimates are...

Loop gain normalization is employed in adaptive filters to control weighting of the filter characteristic updates in order to converge properly to a desired filter characteristic. Filter instability is avoided during intervals that transient or other rapidly pulsating signals are received or inputted by normalizing the update gain with a representation of a so-called fast attack estimate of a prescribed characteristic of the input signal. In one embodiment the fast attack estimate is the maximum...

An emulating data processor includes a host system and an emulating processor with outputs to and inputs from the host system. The emulating processor executes sequences of instructions executable by a PC being emulated, but a host processor independently executes sequences of its instructions which are different from PC instructions. Circuitry monitors the emulating processor outputs and provides information to the host system so that it can emulate the environment of the PC CPU, emulating both...

Methods and apparatuses for updating a forecast model quantifying the marketing of to the demand for a product and/or service are described. An original forecast model created at a reference M is used. An error of the forecast model is determined based on data including an original data and an additional data. At least one parameter is identified to be changed in value in, added to, or removed from the original forecast model. The forecast model is then modified to reduce the error of the foreca...

A simplified cache with automatic updating for use in a memory system. The cache and the main memory receive data from a common input, and when a memory write operation is performed on data stored at a memory location for which there is a corresponding cache location, the data is written simultaneously to the cache and to the main memory. Since a cache location coresponding to a memory location always contains a copy of the data at the memory location, there is no need for dirty bits or valid bi...

In a video terminal comprising a terminal processor communicating with a central processor, and a single-block non-interleaved video memory for storing video information for displaying on the terminal screen, a video update FIFO buffer is provided for buffering video information between the terminal processor and the video memory. The 3-word FIFO buffer is filled during screen trace, and it transfers its contents into the video memory during screen retrace periods. The FIFO buffer permits screen...

A method for detecting high speed data received by a computer and for delaying displaying the receive data, thereby increase the microprocessor time devoted to receiving and storing the input data. Three parameters are utilized for determining when updating the display should be delayed because data input speed is high. First, if the input data is close to filling the computer's receive buffer, the data input speed is high. Second, if the data input port becomes idle, no more data is being input...