A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contac…

Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the …

A method is described for characterizing defects on a test surface of a semiconductor wafer using a confocal-microscope-based automatic defect characterization (ADC) system. The surface to be tested and a reference surface are scanned using a confocal microscope to obtain three-dimensional images of the test and reference surfaces. The test and reference images are converted into sets of geometric constructs, or “primitives,” that are used to approximate features of the images. Next, the sets of…

An apparatus and method of improving impedance matching between a RF signal and a multi-segmented electrode in a plasma reactor powered by the RF signal. The apparatus and method phase shifts the RF signal driving one or more electrode segment of the multi-segmented electrode, amplifies the RF signal, and matches an impedance of the RF signal with an impedance of the electrode segment, where the RF signal is modulated prior to matching of the impedance of the RF signal. The apparatus and method …

An adaptive manufacturing process for a Film Bulk Acoustic Resonator (FBAR) tests the FBAR circuit during manufacturing to determine a resonant frequency thereof. Reactive tuning elements may be adjusted as needed depending on the testing to change the resonant frequency to a desired resonant frequency. In an exemplary embodiment, predetermined masks may be applied to modify the tuning elements.

provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device’s back-gate is self-aligned to the device’s front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enha…

A method and apparatus for determining burn-in reliability from wafer level burn-in are disclosed. The method according to the present invention includes recording the number of failures in each IC die in nonvolatile elements on-chip at points in time over the duration of wafer level burn-in testing. The number of failures in each IC die, along with their associated points in time, may be used to create burn-in reliability curves which are conventionally derived using other processes that may be…

Bright and dark field imaging operations in an optical inspection system occur along substantially the same optical path using the same light source by producing either a circular or an annular laser beam. Multiple beam splitting is achieved through the use of a diffractive optical element having uniform diffraction efficiency. A confocal arrangement for bright field and dark field imaging can be applied with multiple beam scanning for suppressing the signal from under-layers. A scan direction n…

A dielectric film containing LaAlO.sub.3 and method of fabricating a dielectric film contained LaAlO.sub.3 produce a reliable gate dielectric having a thinner equivalent oxide thickness than attainable using SiO.sub.2. The LaAlO.sub.3 gate dielectrics formed are thermodynamically stable such that these gate dielectrics will have minimal reactions with a silicon substrate or other structures during processing. A LaAlO.sub.3 gate dielectric is formed by atomic layer deposition employing a lanthanu…

When a dummy sidewall and source and drain regions are once formed and then the dummy sidewall is removed to extend the source and drain regions, the removal of the dummy sidewall is performed after formation of a protective oxide film on a gate electrode and on the major surfaces of the source and drain regions. This efficiently prevents conventional surface roughness of the upper surface of the gate electrode and the impurity region due to the removal of the dummy sidewall.