A large number of frequent events may be accurately counted by employing a shift register. The values of several bit positions within the shift register are logically combined to generate an input to the shift register. The input is shifted in to alter the register contents whenever an event to be counted occurs. The bit positions for generating the input are selected to produce the longest sequence of nonrepeating patterns possible. The event counter may be implemented in a small area, allowing…

A multiprocessor data processing system includes a plurality of processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. A first processor executes a high speed instruction sequence including a load-type instruction to acquire a promotion bit field within the global promotion facility exclusive of at least a second processor. The request may be made visible to all processors coupled to the interconnect. In response to execution of the …

The address tenure for PCR synchronization operations is redefined to support inclusion of the synchronization data within the address tenure. The bits of a particular field within the address tenure (e.g., the address field) are re-allocated to synchronization data, which is known to be small enough to fit within the unused bits. The address tenure is then broadcasted as a normal address operation and is snooped by all of the processors. The snooping logic is designed to recognize regular/norma…

A selectable interface for interfacing integrated circuit modules is disclosed. The bus interface for interconnecting a first circuit module and a second circuit module includes a transmitter pair located within the first circuit module and a receiver pair located within the second circuit module. The transmitter pair, which can be selectable between a differential mode and a single-ended mode, transmits data from the first circuit module to the second circuit module. The receiver pair, which ca…

A set of local invalidation buses for a highly scalable shared cache memory hierarchy is disclosed. A symmetric multiprocessor data processing system includes multiple processing units. Each of the processing units is associated with a level one cache memory. All the level one cache memories are associated with an imprecisely inclusive level two cache memory. In addition, a group of local invalidation buses is connected between all the level one cache memories and the level two cache memory. The…

A symmetric multiprocessor data processing system having an apparatus for imprecisely tracking cache line inclusivity of a higher level cache is disclosed. The symmetric multiprocessor data processing system includes multiple processing units. Each of the processing units is associated with a level one cache memory. All the level one cache memories are associated with an imprecisely inclusive level two cache memory. The imprecisely inclusive level two cache memory includes a tracking means for i…

A symmetric multiprocessor data processing system having a highly scalable shared cache memory hierarchy is disclosed. The symmetric multiprocessor data processing system includes multiple processing units. Each of the processing units includes a level one cache memory. All the level one cache memories are associated with a level two cache memory. The level two cache memory is non-inclusive of all the level one cache memories. An invalidation bus is connected to all of the level one cache memori…

According to a method of operating a data processing system, one or more monitoring parameter sets are established in a processing unit within the data processing system. The processing unit monitors, in hardware, execution of each of a plurality of schedulable software entities within the processing unit in accordance with a monitoring parameter set among the one or more monitoring parameter sets. The processing unit then reports to software executing in the data processing system utilization o…

Software communicates to a processing unit a classification each of at least one schedulable software entity that the processing unit executes. A resource manager within the processing unit dynamically allocates hardware resources within the processing unit to the schedulable software entity during execution in accordance with the classification. The classification may be retrieved by the software from in data storage, and operating system software may schedule the schedulable software entity fo…

A data processing system includes a global promotion facility containing a plurality of promotion bit fields, an interconnect, and a plurality of processing units coupled to the global promotion facility and to the interconnect. A first processing unit includes an instruction sequencing unit, an execution unit that executes an acquisition instruction to acquire a particular promotion bit field within the global promotion facility, and a promotion awareness facility. In response to the first proc…