An improved display system which includes a central processing unit (CPU) coupled to a display utilizing vertical blanking intervals. A frame buffer memory is coupled to the CPU for storing data representative of color indices for each display pixel. The frame buffer is further coupled to look-up tables (LUTs) for storing color values which are provided through digital/analog converters (DACs) to the display. The CPU updates the contents of the frame buffer and/or LUTs during the vertical blanki…

An adaptive forward differencing apparatus wherein, when rendering curves, calculated x, y values are increased or decreased in order to create values which correspond to the next pixel of the display CRT, such that curves of substantially one pixel increments are continuously and uniformly generated. The apparatus of the present invention also provides circuitry for generating coordinates of display elements which approximate an ideal vector and to define curves, vectors or objects within maxim…

A multi-input logic gate is disclosed having particular application for use as an AND or OR gate in a digital circuit. The OR gate of the present invention includes drive, sense and reference rails. A plurality of input lines are coupled to a gate of a plurality of N-channel transfers disposed between the drive and sense rails, one input line per transistor. The drive rail is coupled to ground through an N-channel transistor whose gate is controlled by the state of a detect line. The sense and r…

A memory architecture having particular application for use in computer systems employing virtual memory techniques. A processor provides row and column addresses to access data stored in a dynamic random access memory (DRAM). The virtual address supplied by the processor includes high and low order bits. In the present embodiment, the high order bits represent a virtual row address and the low order bits represent a real column address. The virtual row address is applied to a memory management …

An improved memory organization for use in a computer display system including a display having a plurality of display pixels for defining images that includes: a frame buffer memory having a plurality of memory cells organized into a matrix, said memory comprising first and second maps wherein the contents of the maps correspond to the pixels and define characteristics of the pixels, the maps being defined along X and Z axes of the matric; reading means coupled to the frame buffer memory for se…

The present invention provides an improved arbitrator for use in allocating access to a common resource coupled to a plurality of data processing devices (“agents”). An arbitrator is coupled between the resource and each of the agents, for selectively enabling individual agents to access the resource in accordance with a predetermined priority hierarchy. The arbitrator, in the presently preferred embodiment, receives request signals transmitted by an agent desiring to access the resource and all…

The present invention discloses apparatus and methods for direct memory access (DMA) having particular application for use in displaying digital images in an animated form on a CRT display. The present invention includes a DMA controller coupled over a bus to a frame buffer. The frame buffer includes one or more bit maps representative of the display. A block of memory within the frame buffer is mapped onto corresponding picture elements (pixels) on the display. The frame buffer continuously sca…

A computer memory architecture is most advantageously used in conjunction with a digital computer, to provide an improved high speed graphics display capability. Data representative of digital images to be displayed is generated and/or manipulated by a display processor and stored within a selected portion of the display processor’s main memory. Subsequent modifications to the stored image are effectuated by the display processor reading the data from its main memory, performing appropriate oper…

The present invention provides apparatus and methods which are most advantageously used in conjunction with a computer display system incorporating the use of a Z-buffer to provide three dimensional hidden surface elimination. A buffer memory is provided which is sufficiently large such that each display element (pixel) on the display is represented by a 16-bit Z value. The Z value corresponds to the Z axis depth of the object at the particular point corresponding to the pixel. The buffer compri…

Apparatus and methods for displaying two and three dimensional graphics within a plurality of windows on a display system. The display system includes a central processing unit (CPU) which provides RGB data to a bit-mapped display memory coupled to a cathode ray tube (CRT) display. A Z-buffer memory is provided with a Z-value for each RGB data point corresponding to a point on the object to be displayed. The Z-buffer is organized such that the value of the entire n bit buffer (0 through 2.sup. n…