A multiplexed memory request interface capable of staging one memory access request while an immediately previously received memory access address request is being received and processed in the memory, and employing a common memory access path and other common circuitry for both address requests.

Instruction SIGNAL PROCESSOR, devoted to initiation of input/output control between an initiating data processor unit and a respondent unit, is used to implement dispatching operations by transferral of Operation Request Block (ORB) storage space addressing intelligence and interruption priority level intelligence from the initiating unit to the respondent unit. The priority level intelligence is prepared by the initiating unit in said space and thereby implicitly conveyed with the addressing in…

An access request selecting circuit for selectively accepting access request signals produced from a plurality of access request sources. Different series of recurrent time intervals are assigned to the access request sources. When a memory request signal is supplied from an access request source in a series of recurrent time intervals which are assigned to the access request source such a memory request signal is accepted. At this time, if an attendant signal produced in association with the me…

Multiple usage requests for a common resource, such as a memory system, are given usage priorities by a multiple request arbitration circuit. Priority is given to a predetermined one of the input signals occurring prior to any one of the remaining input signals and priority is also given to the one input signal if it occurs within a predetermined interval subsequent to any one of the remaining input signals. The circuit also provides for the suppression of voltage transients which may occur upon…

A memory request arbitrator is provided for selecting one of a plurality of requesting devices, such as microprocessors, which may make a request to access a memory device common to the plurality of requestors. Requests from the devices are applied in common as a portion of an address to a read only memory, a priority sequencer providing another portion of the address. The read only memory provides a selection signal to the selected requestor. The priority sequencer is periodically updated to th…

Storage access requests are forwarded from plural input/output channels to shared main storage. An address word in each request designates the identity of the source channel (CHID) and “destination” address (of a doubleword space in storage relative to which one, two or four “data” words shall be transferred). EOT tag signal provides demarcation of requests and also uniquely identifies “1-wide” input (Store) requests. Quadword (QW) tag, presented with “4-wide” requests, enables the storage acces…

In one embodiment, a method may include, if an amount of data requested to be transferred by a data transfer request according to a first protocol exceeds a maximum data transfer amount permitted to be requested by a single data transfer request according to a second protocol, generating one data transfer request according to the second protocol and a data structure, and modifying, at least in part, another data structure. This data transfer request may request transfer of a portion of the data….

An option request protocol allows dynamic negotiation of options between a host computer and a control unit of a computer network. The protocol is manifested as an exchange of novel control messages over a control link used to establish logical data links for communication between the host and control unit. The options negotiated by the control message exchange generally pertain to additional functions performed by the control unit or host, or additional parameters for communication over the dat…

To reduce latency for priority requests in a bus system, non-priority requests to a bus device are separated from priority requests so that the priority requests can be processed before the non-priority requests. Priority requests are transferred over a priority request bus. Standard non-priority requests are sent over a shared bus coupled to several bus devices. One of the bus devices contains a request buffer to receive non-priority requests from the shared bus and a priority buffer to receive…

An interlock arrangement in which each service request path comprises two inverter gates between an input and an output with a junction between the gates. Cross-coupling circuits are coupled from each junction to every other junction in each direction, each comprising an inverting gate in series with a diode. The diodes are normally reverse biased. A first to arrive request signal is forwarded to its output, and a later signal at any other input causes one diode to conduct and clamp the junction…