A cover for a folding lawn chair is provided to allow a person to conveniently carry the folding lawn chair as well as to increase comfort when the person is using the lawn chair. The cover may include an enveloped or flapped portion on each on its ends into which each end of the lawn chair can be situated. The cover thus remains in position on the lawn regardless of wind and movement by the user. The cover further includes a strap to accommodate convenient carrying of the lawn chair. The cover …

A condom case is provided that houses one or more condoms within an enclosure having two distinct and interdependent locking mechanisms. Two separate keys must be employed simultaneously to disengage the locking mechanisms and open the condom case. The condom case pragmatically protects the condom while symbolically promoting the concepts of mutual consent, fidelity, dignity, commitment and intimacy. The keys may be worn around the necks of each individual as an overt talisman of their exclusive…

A game call is disclosed that incorporates two frictional striking surfaces of both slate and glass on a common base to simulate sounds of wild game having varying tone, pitch, texture and frequency. The frictional striking surfaces are provided on one or more non-opposite sides of the base. The use of two distinct and different striking surfaces allows the operator to imitate the calls of different game animals with a minimum amount of movement. The operator can easily compare and determine whi…

An eyewear apparatus for use in sporting activities allows convenient view and control of a data display device by an athlete. A data display implant device including a data display and a lens is incorporated in association with sporting eyewear such as a pair of swimming goggles. The data display implant device may be an integral unit of the eyewear or may be a retrofit unit. A motion sensitive switch may also be included to cause freezing of the display device following each flip-turn of the s…

A processing unit is provided that generates an address signal which specifies data on a per-byte basis and that further generates a set of byte enable signals which specify enabled bytes relative to the addressed byte. Both the byte enable signals and the address signal are provided to a memory control unit. The processing unit can thereby generate a single memory access to a misaligned memory address, while still specifying a variable number of enabled bytes. A control input provided to the pr…

A microprocessor includes a programmable thermal sensor incorporated on an associated semiconductor die for generating a signal indicative of the temperature of the semiconductor die. The control signal is provided to a frequency synthesizer which controls the frequency of the CPU clock signal. The frequency synthesizer is dynamically controlled such that the frequency of the CPU clock signal is varied to run at an optimal frequency while preventing the microprocessor from overheating. In one em…

A system is disclosed for merging data from two separate registers at different locations in a computer system. A floppy drive controller is provided as part of a companion chip located separately from an IDE drive controller. Both controllers include a data register with the same address to make the system compatible with prior BIOS programs. The register in the floppy controller includes a DSK CHG bit as bit D7 of a direct input register (DIR), which is obtained from the DSK CHG# signal from t…

A symmetrical multiprocessing system is provided that includes centralized interrupt control unit. The interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt control unit advantageously allows for the expansion of each interrupt pin by setting the interrupt control unit in a cascade mode. Furthermore, the central control unit is responsive to specialized interrupt cycles which allows I/O devices and/or bus bridge devices to ini…

A symmetrical multiprocessing system is provided that includes centralized interrupt control unit. The interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt control unit advantageously allows for the expansion of each interrupt pin by setting the interrupt control unit in a cascade mode. Furthermore, the central control unit is responsive to specialized interrupt cycles which allows I/O devices and/or bus bridge devices to ini…

An integrated processor that employs a bus interface unit to accommodate high performance data transfers via an external peripheral interconnect bus with multiplexed address/data lines. The peripheral interconnect bus, which may be a PCI standard bus, accommodates data transfers between an internal bus of the integrated processor and PCI peripheral devices. The integrated processor further includes a sub-bus control unit that generates a set of side-band control signals that allow the external d…